VLSI Implementation of Fully Parallel and CSD FIR Filter Architecture Using Clock Gating. International Journal of Scientific Research in Science and Technology, [S. l.], v. 12, n. 1, p. 658–666, 2025. Disponível em: https://www.ijsrst.technoscienceacademy.com/index.php/home/article/view/IJSRST25121205. Acesso em: 29 jul. 2025.