Enhancing Power Efficiency in FIR Filter VLSI Architecture for Seismic Signal Processing with Clock Gating. International Journal of Scientific Research in Science and Technology, [S. l.], v. 12, n. 2, p. 866–874, 2025. Disponível em: https://www.ijsrst.technoscienceacademy.com/index.php/home/article/view/IJSRST251222634. Acesso em: 29 jul. 2025.