VLSI Implementation of Fully Parallel and CSD FIR Filter Architecture Using Clock Gating. Int J Sci Res Sci & Technol [Internet]. 2025 Feb. 23 [cited 2025 Jul. 29];12(1):658-66. Available from: https://www.ijsrst.technoscienceacademy.com/index.php/home/article/view/IJSRST25121205